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fusesoc run --target=sim swervolf with Verilator=3.918 #40

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nicolast0604 opened this issue Jul 22, 2021 · 2 comments
Open

fusesoc run --target=sim swervolf with Verilator=3.918 #40

nicolast0604 opened this issue Jul 22, 2021 · 2 comments

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@nicolast0604
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%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:403: Define or directive not defined: RV_BTB_ADDR_HI %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:403: Define or directive not defined: RV_BTB_BTAG_SIZE
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418: Define or directive not defined: RV_BTB_ADDR_HI %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418: syntax error, unexpected ':', expecting TYPE-IDENTIFIER %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:418: Define or directive not defined: RV_BTB_ADDR_LO
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:421: Define or directive not defined: RV_BTB_ADDR_HI %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:421: Define or directive not defined: RV_BTB_ADDR_LO
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:421: Define or directive not defined: RV_BTB_INDEX1_HI %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:421: Define or directive not defined: RV_BTB_INDEX1_LO
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:424: Define or directive not defined: RV_BTB_INDEX2_HI %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:424: Define or directive not defined: RV_BTB_INDEX2_LO
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:427: Define or directive not defined: RV_BTB_INDEX3_HI %Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:427: Define or directive not defined: RV_BTB_INDEX3_LO
%Error: Exiting due to too many errors encountered; --error-limit=50
%Error: Command Failed /tools/verilator/3.918/bin/verilator_bin -f swervolf_0.7.3.vc --trace -Wno-fatal
Makefile:16: recipe for target 'Vswervolf_core_tb.mk' failed
make: *** [Vswervolf_core_tb.mk] Error 10
ERROR: Failed to build ::swervolf:0.7.3 : 'make' exited with an error code

@olofk
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olofk commented Aug 10, 2021

Verilator 3.918 is too old unfortunately. I see now that the instructions are out of date. I don't remember right now which is the minimum version that works, but I'm using 4.034 myself and that seems to be new enough at least

@fasih0001
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fusesoc run --target=sim veerwolf with Verilator = 4.106 and fusesoc = 2.2.1

I'm also experiencing a similar error and precisely i do not understand why this error is occurring. I've run the command

fusesoc run --target=sim veerwolf

After running the command, the program proceeds fine till this point :

INFO: Preparing ::cdc_utils:0.1-r1
INFO: Preparing chipsalliance.org:cores:VeeR_EH1:1.9
INFO: Preparing fusesoc:utils:generators:0.1.7
INFO: Preparing ::jtag_vpi:0-r5
INFO: Preparing pulp-platform.org::common_cells:1.20.0
INFO: Preparing ::simple_spi:1.6.1
INFO: Preparing ::uart16550:1.5.5-r1
INFO: Preparing ::verilog-arbiter:0-r3
INFO: Preparing ::wb_common:1.0.3
INFO: Preparing pulp-platform.org::axi:0.25.0
INFO: Preparing ::wb_intercon:1.2.2-r1
INFO: Preparing ::veerwolf:0.7.5
INFO: Generating ::veerwolf-intercon:0.7.5
Found master ifu
Found master lsu
Found master sb
Found slave io
Found slave ram
================================================================================
INFO: Generating ::veerwolf-version:0.7.5
INFO: Generating ::veerwolf-wb_intercon:0.7.5
Found master io
Found slave rom
Found slave sys
Found slave spi_flash
Found slave uart
================================================================================
INFO: Generating ::veerwolf-veer_eh1_default_config:0.7.5
INFO: Setting up project
INFO: Building simulation model
INFO: verilator -f veerwolf_0.7.5.vc --trace -Wno-fatal

Afterwards the following errors occurs :

make  -f Vveerwolf_core_tb.mk
make[1]: Entering directory '/home/ubuntu/Desktop/RVfpgaSoC/Labs/LabProjects/VeeRwolf/build/veerwolf_0.7.5/sim-verilator'
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Iconfig -Isrc/chipsalliance.org_cores_VeeR_EH1_1.9/design/include -Isrc/jtag_vpi_0-r5 -Isrc/pulp-platform.org__common_cells_1.20.0/include -Isrc/uart16550_1.5.5-r1/rtl/verilog -Isrc/wb_common_1.0.3 -Isrc/pulp-platform.org__axi_0.25.0/include -Isrc/veerwolf-intercon_0.7.5 -Isrc/veerwolf-wb_intercon_0.7.5  -std=gnu++14 -Os -c -o jtagServer.o src/jtag_vpi_0-r5/jtagServer.cpp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Iconfig -Isrc/chipsalliance.org_cores_VeeR_EH1_1.9/design/include -Isrc/jtag_vpi_0-r5 -Isrc/pulp-platform.org__common_cells_1.20.0/include -Isrc/uart16550_1.5.5-r1/rtl/verilog -Isrc/wb_common_1.0.3 -Isrc/pulp-platform.org__axi_0.25.0/include -Isrc/veerwolf-intercon_0.7.5 -Isrc/veerwolf-wb_intercon_0.7.5  -std=gnu++14 -Os -c -o jtag_common.o src/jtag_vpi_0-r5/jtag_common.c
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Iconfig -Isrc/chipsalliance.org_cores_VeeR_EH1_1.9/design/include -Isrc/jtag_vpi_0-r5 -Isrc/pulp-platform.org__common_cells_1.20.0/include -Isrc/uart16550_1.5.5-r1/rtl/verilog -Isrc/wb_common_1.0.3 -Isrc/pulp-platform.org__axi_0.25.0/include -Isrc/veerwolf-intercon_0.7.5 -Isrc/veerwolf-wb_intercon_0.7.5  -std=gnu++14 -Os -c -o tb.o src/veerwolf_0.7.5/tb/tb.cpp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Iconfig -Isrc/chipsalliance.org_cores_VeeR_EH1_1.9/design/include -Isrc/jtag_vpi_0-r5 -Isrc/pulp-platform.org__common_cells_1.20.0/include -Isrc/uart16550_1.5.5-r1/rtl/verilog -Isrc/wb_common_1.0.3 -Isrc/pulp-platform.org__axi_0.25.0/include -Isrc/veerwolf-intercon_0.7.5 -Isrc/veerwolf-wb_intercon_0.7.5  -std=gnu++14 -Os -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
make[1]: Leaving directory '/home/ubuntu/Desktop/RVfpgaSoC/Labs/LabProjects/VeeRwolf/build/veerwolf_0.7.5/sim-verilator'

ERROR: %Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:85:27: Operator ASSIGN expects 74 bits on the Assign RHS, but Assign RHS's SEL generates 72 bits.
                                                                             : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.gen_id_prepend[0].i_id_prepend
   85 |         mst_aw_chans_o[i] = slv_aw_chans_i[i];
      |                           ^
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:86:27: Operator ASSIGN expects 68 bits on the Assign RHS, but Assign RHS's SEL generates 66 bits.
                                                                             : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.gen_id_prepend[0].i_id_prepend
   86 |         mst_ar_chans_o[i] = slv_ar_chans_i[i];
      |                           ^
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:93:29: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's SEL generates 9 bits.
                                                                             : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.gen_id_prepend[0].i_id_prepend
   93 |     assign slv_b_chans_o[i] = mst_b_chans_i[i];
      |                             ^
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:94:29: Operator ASSIGNW expects 72 bits on the Assign RHS, but Assign RHS's SEL generates 74 bits.
                                                                             : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.gen_id_prepend[0].i_id_prepend
   94 |     assign slv_r_chans_o[i] = mst_r_chans_i[i];
      |                             ^
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:460:55: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 2 bits.
                                                                         : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux
  460 |         if (aw_valid && (slv_aw_chan_select.aw_select == i)) begin
      |                                                       ^~
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:467:40: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'w_select' generates 2 bits.
                                                                         : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux
  467 |         if (!w_fifo_empty && (w_select == i)) begin
      |                                        ^~
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:479:55: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 2 bits.
                                                                         : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux
  479 |         if (ar_valid && (slv_ar_chan_select.ar_select == i)) begin
      |                                                       ^~
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:126:12: Operator CASE expects 8 bits on the Case Item, but Case Item's CONST '4'h1' generates 4 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  126 |     unique case (len)
      |            ^~~~
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:126:12: Operator CASE expects 8 bits on the Case Item, but Case Item's CONST '4'h3' generates 4 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  126 |     unique case (len)
      |            ^~~~
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:126:12: Operator CASE expects 8 bits on the Case Item, but Case Item's CONST '4'h7' generates 4 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  126 |     unique case (len)
      |            ^~~~
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:126:12: Operator CASE expects 8 bits on the Case Item, but Case Item's CONST '4'hf' generates 4 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  126 |     unique case (len)
      |            ^~~~
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:163:55: Operator ADD expects 128 bits on the LHS, but LHS's VARREF 'len' generates 8 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  163 |         ret_addr = ret_addr - (num_bytes(size) * (len + 1));
      |                                                       ^
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:162:81: Operator ADD expects 128 bits on the LHS, but LHS's VARREF 'len' generates 8 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  162 |       if (burst == BURST_WRAP && ret_addr >= wrp_bond + (num_bytes(size) * (len + 1))) begin
      |                                                                                 ^
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:174:27: Operator DIV expects 128 bits on the RHS, but RHS's VARREF 'strobe_width' generates 16 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  174 |     return _addr - (_addr / strobe_width) * strobe_width;
      |                           ^
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:174:5: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's SUB generates 128 bits.
                                                                      : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  174 |     return _addr - (_addr / strobe_width) * strobe_width;
      |     ^~~~~~
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:182:58: Operator SUB expects 128 bits on the LHS, but LHS's FUNCREF 'num_bytes' generates 16 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  182 |       return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width;
      |                                                          ^
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:182:71: Operator DIV expects 128 bits on the RHS, but RHS's VARREF 'strobe_width' generates 16 bits.
                                                                       : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  182 |       return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width;
      |                                                                       ^
%Warning-WIDTH: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:182:7: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's SUB generates 128 bits.
                                                                      : ... In instance veerwolf_core_tb.veerwolf.uart16550_0.regs.transmitter
  182 |       return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width;
      |       ^~~~~~
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:148:48: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS's SHIFTR generates 20 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  148 | wire [VALID_ADDR_WIDTH-1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
      |                                                ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:149:48: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS's SHIFTR generates 20 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  149 | wire [VALID_ADDR_WIDTH-1:0] s_axi_araddr_valid = s_axi_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
      |                                                ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:150:45: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS's SHIFTR generates 20 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  150 | wire [VALID_ADDR_WIDTH-1:0] read_addr_valid = read_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
      |                                             ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:151:46: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS's SHIFTR generates 20 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  151 | wire [VALID_ADDR_WIDTH-1:0] write_addr_valid = write_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
      |                                              ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:201:48: Operator LT expects 32 bits on the LHS, but LHS's VARREF 's_axi_awsize' generates 3 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  201 |                 write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH);
      |                                                ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:201:69: Operator COND expects 32 bits on the Conditional True, but Conditional True's VARREF 's_axi_awsize' generates 3 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  201 |                 write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH);
      |                                                                     ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:201:33: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS's COND generates 32 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  201 |                 write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH);
      |                                 ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:304:47: Operator LT expects 32 bits on the LHS, but LHS's VARREF 's_axi_arsize' generates 3 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  304 |                 read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH);
      |                                               ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:304:68: Operator COND expects 32 bits on the Conditional True, but Conditional True's VARREF 's_axi_arsize' generates 3 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  304 |                 read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH);
      |                                                                    ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/axi_ram.v:304:32: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS's COND generates 32 bits.
                                                       : ... In instance veerwolf_core_tb.ram
  304 |                 read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH);
      |                                ^
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/veerwolf_core.v:170:8: Input port connection 'i_awid' expects 7 bits on the pin connection, but pin connection's VARREF 'io_awid' generates 6 bits.
                                                            : ... In instance veerwolf_core_tb.veerwolf
  170 |       .i_awid      (io_awid),
      |        ^~~~~~
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/veerwolf_core.v:175:8: Input port connection 'i_arid' expects 7 bits on the pin connection, but pin connection's VARREF 'io_arid' generates 6 bits.
                                                            : ... In instance veerwolf_core_tb.veerwolf
  175 |       .i_arid      (io_arid),
      |        ^~~~~~
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/veerwolf_core.v:184:8: Output port connection 'o_bid' expects 7 bits on the pin connection, but pin connection's VARREF 'io_bid' generates 6 bits.
                                                            : ... In instance veerwolf_core_tb.veerwolf
  184 |       .o_bid       (io_bid),
      |        ^~~~~
%Warning-WIDTH: src/veerwolf_0.7.5/rtl/veerwolf_core.v:190:8: Output port connection 'o_rid' expects 7 bits on the pin connection, but pin connection's VARREF 'io_rid' generates 6 bits.
                                                            : ... In instance veerwolf_core_tb.veerwolf
  190 |       .o_rid       (io_rid),
      |        ^~~~~
%Warning-UNSIGNED: src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:208:37: Comparison is constant due to unsigned arithmetic
                                                                                       : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.gen_demux.i_b_mux
  208 |           assign upper_mask[i] = (i >  rr_q) ? req_d[i] : 1'b0;
      |                                     ^
%Warning-UNSIGNED: src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:209:37: Comparison is constant due to unsigned arithmetic
                                                                                       : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.gen_demux.i_b_mux
  209 |           assign lower_mask[i] = (i <= rr_q) ? req_d[i] : 1'b0;
      |                                     ^~
%Warning-CASEINCOMPLETE: src/veerwolf_0.7.5/rtl/axi_ram.v:193:5: Case values incompletely covered (example pattern 0x3)
                                                               : ... In instance veerwolf_core_tb
  193 |     case (write_state_reg)
      |     ^~~~
%Warning-CASEINCOMPLETE: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:216:12: Case values incompletely covered (example pattern 0xc)
                                                                                : ... In instance axi_pkg
  216 |     unique case (mtype)
      |            ^~~~
%Warning-CASEINCOMPLETE: src/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv:234:12: Case values incompletely covered (example pattern 0xc)
                                                                                : ... In instance axi_pkg
  234 |     unique case (mtype)
      |            ^~~~
%Warning-UNOPTFLAT: src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:467:58: Signal unoptimizable: Feedback to clock or circular logic: 'veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.__Vcellout__LEVEL[0].COMPARE[0].cmp_l1__out_id'
                                                                                      : ... In instance veerwolf_core_tb.veerwolf
  467 |                         output logic [ID_BITS-1:0]       out_id,
      |                                                          ^~~~~~
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:467:58:      Example path: veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.__Vcellout__LEVEL[0].COMPARE[0].cmp_l1__out_id
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:328:31:      Example path: ASSIGNW
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:309:69:      Example path: veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.level_intpend_id
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:477:44:      Example path: ASSIGNW
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:467:58:      Example path: veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.__Vcellout__LEVEL[0].COMPARE[0].cmp_l1__out_id
%Warning-UNOPTFLAT: src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:468:61: Signal unoptimizable: Feedback to clock or circular logic: 'veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.__Vcellout__LEVEL[0].COMPARE[0].cmp_l1__out_priority'
                                                                                      : ... In instance veerwolf_core_tb.veerwolf
  468 |                         output logic [INTPRIORITY_BITS-1:0] out_priority
      |                                                             ^~~~~~~~~~~~
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:468:61:      Example path: veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.__Vcellout__LEVEL[0].COMPARE[0].cmp_l1__out_priority
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:329:31:      Example path: ASSIGNW
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:308:69:      Example path: veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.level_intpend_w_prior_en
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:474:20:      Example path: ASSIGNW
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:472:9:      Example path: veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.LEVEL[0].COMPARE[0].cmp_l1.a_is_lt_b
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:479:44:      Example path: ASSIGNW
                    src/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv:468:61:      Example path: veerwolf_core_tb.veerwolf.rvtop.veer.pic_ctrl_inst.__Vcellout__LEVEL[0].COMPARE[0].cmp_l1__out_priority
%Warning-UNOPTFLAT: src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:48:36: Signal unoptimizable: Feedback to clock or circular logic: 'veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.mst_reqs_o'
                                                                            : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux
   48 |   output req_t    [NoMstPorts-1:0] mst_reqs_o,
      |                                    ^~~~~~~~~~
                    src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:48:36:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.mst_reqs_o
                    src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:151:8:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:50:54:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.slv_reqs
                    src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:181:30:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:57:55:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.mst_reqs
                    src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:175:10:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:85:36:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.slv_ar_valids
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:157:27:      Example path: ASSIGNW
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:138:33:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.i_ar_arbiter.gen_arbiter.req_d
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:269:24:      Example path: ASSIGNW
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:257:15:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.i_ar_arbiter.gen_arbiter.gen_levels[1].gen_level[0].sel
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:273:38:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:85:51:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.slv_ar_readies
                    src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:161:10:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:59:38:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.slv_resps_o
                    src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:215:8:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:58:55:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.mst_resps
                    src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:182:30:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:51:54:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.slv_resps
                    src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:490:36:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:109:31:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.gen_demux.mst_b_valids
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:157:27:      Example path: ASSIGNW
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:138:33:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.gen_demux.i_b_mux.gen_arbiter.req_d
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:269:24:      Example path: ASSIGNW
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:257:15:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.gen_demux.i_b_mux.gen_arbiter.gen_levels[1].gen_level[0].sel
                    src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:273:38:      Example path: ASSIGNW
                    src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:109:51:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.gen_demux.mst_b_readies
                    src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:450:5:      Example path: ALWAYS
                    src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:48:36:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_slv_port_demux[0].i_axi_demux.mst_reqs_o
%Warning-UNOPTFLAT: src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:59:30: Signal unoptimizable: Feedback to clock or circular logic: 'veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.i_aw_arbiter.gen_arbiter.gen_int_rr.gen_fair_arb.i_lzc_lower.gen_lzc.sel_nodes'
                                                                               : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux
   59 |     logic [2**NumLevels-1:0] sel_nodes;
      |                              ^~~~~~~~~
                    src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:59:30:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.i_aw_arbiter.gen_arbiter.gen_int_rr.gen_fair_arb.i_lzc_lower.gen_lzc.sel_nodes
                    src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:98:48:      Example path: ASSIGNW
                    src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:59:30:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.i_aw_arbiter.gen_arbiter.gen_int_rr.gen_fair_arb.i_lzc_lower.gen_lzc.sel_nodes
%Warning-UNOPTFLAT: src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:60:45: Signal unoptimizable: Feedback to clock or circular logic: 'veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.i_aw_arbiter.gen_arbiter.gen_int_rr.gen_fair_arb.i_lzc_upper.gen_lzc.index_nodes'
                                                                               : ... In instance veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux
   60 |     logic [2**NumLevels-1:0][NumLevels-1:0] index_nodes;
      |                                             ^~~~~~~~~~~
                    src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:60:45:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.i_aw_arbiter.gen_arbiter.gen_int_rr.gen_fair_arb.i_lzc_upper.gen_lzc.index_nodes
                    src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:100:50:      Example path: ASSIGNW
                    src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:60:45:      Example path: veerwolf_core_tb.veerwolf.axi_intercon.axi_xbar.gen_mst_port_mux[0].i_axi_mux.gen_mux.i_aw_arbiter.gen_arbiter.gen_int_rr.gen_fair_arb.i_lzc_upper.gen_lzc.index_nodes
/usr/local/share/verilator/include/verilated.cpp: In function ‘IData VL_FGETS_NI(std::string&, IData)’:
/usr/local/share/verilator/include/verilated.cpp:1303:36: error: ‘numeric_limits’ is not a member of ‘std’
 1303 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
      |                                    ^~~~~~~~~~~~~~
/usr/local/share/verilator/include/verilated.cpp:1303:57: error: expected primary-expression before ‘>’ token
 1303 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
      |                                                         ^
/usr/local/share/verilator/include/verilated.cpp:1303:60: error: ‘::max’ has not been declared; did you mean ‘std::max’?
 1303 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
      |                                                            ^~~
      |                                                            std::max
In file included from /usr/include/c++/11/algorithm:62,
                 from /usr/local/share/verilator/include/verilated_heavy.h:29,
                 from /usr/local/share/verilator/include/verilated_imp.h:29,
                 from /usr/local/share/verilator/include/verilated.cpp:25:
/usr/include/c++/11/bits/stl_algo.h:3467:5: note: ‘std::max’ declared here
 3467 |     max(initializer_list<_Tp> __l, _Compare __comp)
      |     ^~~
make[1]: *** [/usr/local/share/verilator/include/verilated.mk:241: verilated.o] Error 1
make: *** [Makefile:13: Vveerwolf_core_tb] Error 2

ERROR: Failed to build ::veerwolf:0.7.5 : '['make']' exited with an error: 2

Can someone help me figure out why this error occurs.

Thanks!

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