Investigating cache performance with burst wrap reads

[jeras]

This is not a bug report, I would like some help reading the implementation.
I would like to study the data cache and memory controller subsystem.

The aim of my research is to investigate how the order (incrementing/decrementing) of stack access sequences affects performance on a cache miss, if the cache requests data from the memory controller as a wrapped burst.

For now I was only able to find this code, where the burst is defined as INCR, but the length is a single beat.
This is not really a burst, and I think this is because the request here is done by the load/store unit and not the cache.
https://github.com/chipsalliance/Cores-SweRV/blob/master/design/lsu/lsu_bus_buffer.sv#L879-L880

Could somebody help me find the cache code related to AXI4 burst accesses?