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mac.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#include "cam.h"
#include "debug.h"
#include "fw.h"
#include "mac.h"
#include "ps.h"
#include "reg.h"
#include "util.h"
int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx,
enum rtw89_mac_hwmod_sel sel)
{
u32 val, r_val;
if (sel == RTW89_DMAC_SEL) {
r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN);
val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN);
} else if (sel == RTW89_CMAC_SEL && mac_idx == 0) {
r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN);
val = B_AX_CMAC_EN;
} else if (sel == RTW89_CMAC_SEL && mac_idx == 1) {
r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND);
val = B_AX_CMAC1_FEN;
} else {
return -EINVAL;
}
if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD ||
(val & r_val) != val)
return -EFAULT;
return 0;
}
int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
{
u8 lte_ctrl;
int ret;
ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
if (ret)
rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset);
return ret;
}
int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
{
u8 lte_ctrl;
int ret;
ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
if (ret)
rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset);
*val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
return ret;
}
static
int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)
{
u32 ctrl_reg, data_reg, ctrl_data;
u32 val;
int ret;
switch (ctrl->type) {
case DLE_CTRL_TYPE_WDE:
ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL;
data_reg = R_AX_WDE_DBG_FUN_INTF_DATA;
ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) |
FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) |
B_AX_WDE_DFI_ACTIVE;
break;
case DLE_CTRL_TYPE_PLE:
ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL;
data_reg = R_AX_PLE_DBG_FUN_INTF_DATA;
ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) |
FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) |
B_AX_PLE_DFI_ACTIVE;
break;
default:
rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
return -EINVAL;
}
rtw89_write32(rtwdev, ctrl_reg, ctrl_data);
ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE),
1, 1000, false, rtwdev, ctrl_reg);
if (ret) {
rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",
ctrl_reg, ctrl_data);
return ret;
}
ctrl->out_data = rtw89_read32(rtwdev, data_reg);
return 0;
}
static int dle_dfi_quota(struct rtw89_dev *rtwdev,
struct rtw89_mac_dle_dfi_quota *quota)
{
struct rtw89_mac_dle_dfi_ctrl ctrl;
int ret;
ctrl.type = quota->dle_type;
ctrl.target = DLE_DFI_TYPE_QUOTA;
ctrl.addr = quota->qtaid;
ret = dle_dfi_ctrl(rtwdev, &ctrl);
if (ret) {
rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
return ret;
}
quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data);
quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data);
return 0;
}
static int dle_dfi_qempty(struct rtw89_dev *rtwdev,
struct rtw89_mac_dle_dfi_qempty *qempty)
{
struct rtw89_mac_dle_dfi_ctrl ctrl;
u32 ret;
ctrl.type = qempty->dle_type;
ctrl.target = DLE_DFI_TYPE_QEMPTY;
ctrl.addr = qempty->grpsel;
ret = dle_dfi_ctrl(rtwdev, &ctrl);
if (ret) {
rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
return ret;
}
qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data);
return 0;
}
static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev)
{
rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
}
static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev)
{
struct rtw89_mac_dle_dfi_qempty qempty;
struct rtw89_mac_dle_dfi_quota quota;
struct rtw89_mac_dle_dfi_ctrl ctrl;
u32 val, not_empty, i;
int ret;
qempty.dle_type = DLE_CTRL_TYPE_PLE;
qempty.grpsel = 0;
qempty.qempty = ~(u32)0;
ret = dle_dfi_qempty(rtwdev, &qempty);
if (ret)
rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
else
rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) {
if (!(not_empty & BIT(0)))
continue;
ctrl.type = DLE_CTRL_TYPE_PLE;
ctrl.target = DLE_DFI_TYPE_QLNKTBL;
ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) |
FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i);
ret = dle_dfi_ctrl(rtwdev, &ctrl);
if (ret)
rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
else
rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i,
FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK,
ctrl.out_data));
}
quota.dle_type = DLE_CTRL_TYPE_PLE;
quota.qtaid = 6;
ret = dle_dfi_quota(rtwdev, "a);
if (ret)
rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
else
rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
quota.rsv_pgnum, quota.use_pgnum);
val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n",
FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val));
rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n",
FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val));
dump_err_status_dispatcher(rtwdev);
}
static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
enum mac_ax_err_info err)
{
u32 dbg, event;
dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);
event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg);
switch (event) {
case MAC_AX_L0_TO_L1_RX_QTA_LOST:
rtw89_info(rtwdev, "quota lost!\n");
rtw89_mac_dump_qta_lost(rtwdev);
break;
default:
break;
}
}
static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
enum mac_ax_err_info err)
{
u32 dmac_err, cmac_err;
if (err != MAC_AX_ERR_L1_ERR_DMAC &&
err != MAC_AX_ERR_L0_PROMOTE_TO_L1)
return;
rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR);
rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err);
dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err);
if (dmac_err) {
rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ",
rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG));
rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n",
rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG));
}
if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ",
rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n",
rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
}
if (dmac_err & B_AX_WSEC_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n",
rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
}
if (dmac_err & B_AX_MPDU_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ",
rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n",
rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ",
rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n",
rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
}
if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ",
rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n",
rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
}
if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
dump_err_status_dispatcher(rtwdev);
}
if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
}
if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
dump_err_status_dispatcher(rtwdev);
}
if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
}
if (dmac_err & B_AX_DISPATCH_ERR_FLAG)
dump_err_status_dispatcher(rtwdev);
if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) {
rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR));
rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
}
if (dmac_err & BIT(11)) {
rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
}
if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR));
rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n",
rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR));
}
if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ",
rtw89_read32(rtwdev, R_AX_PTCL_IMR0));
rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
}
if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n",
rtw89_read32(rtwdev, R_AX_DLE_CTRL));
}
if (cmac_err & B_AX_PHYINTF_ERR_IND) {
rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR));
}
if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ",
rtw89_read32(rtwdev, R_AX_TXPWR_IMR));
rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
}
if (cmac_err & B_AX_WMAC_RX_ERR_IND) {
rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ",
rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n",
rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
}
if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ",
rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n",
rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
}
rtwdev->hci.ops->dump_err_status(rtwdev);
if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
rtw89_mac_dump_l0_to_l1(rtwdev, err);
rtw89_info(rtwdev, "<---\n");
}
u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
{
u32 err;
int ret;
ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000,
false, rtwdev, R_AX_HALT_C2H_CTRL);
if (ret) {
rtw89_warn(rtwdev, "Polling FW err status fail\n");
return ret;
}
err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
rtw89_fw_st_dbg_dump(rtwdev);
rtw89_mac_dump_err_status(rtwdev, err);
return err;
}
EXPORT_SYMBOL(rtw89_mac_get_err_status);
int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
{
u32 halt;
int ret = 0;
if (err > MAC_AX_SET_ERR_MAX) {
rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
return -EINVAL;
}
ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000,
100000, false, rtwdev, R_AX_HALT_H2C_CTRL);
if (ret) {
rtw89_err(rtwdev, "FW doesn't receive previous msg\n");
return -EFAULT;
}
rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
return 0;
}
EXPORT_SYMBOL(rtw89_mac_set_err_status);
const struct rtw89_hfc_prec_cfg rtw89_hfc_preccfg_pcie = {
2, 40, 0, 0, 1, 0, 0, 0
};
EXPORT_SYMBOL(rtw89_hfc_preccfg_pcie);
static int hfc_reset_param(struct rtw89_dev *rtwdev)
{
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
struct rtw89_hfc_param_ini param_ini = {NULL};
u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
switch (rtwdev->hci.type) {
case RTW89_HCI_TYPE_PCIE:
param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
param->en = 0;
break;
default:
return -EINVAL;
}
if (param_ini.pub_cfg)
param->pub_cfg = *param_ini.pub_cfg;
if (param_ini.prec_cfg) {
param->prec_cfg = *param_ini.prec_cfg;
rtwdev->hal.sw_amsdu_max_size =
param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT;
}
if (param_ini.ch_cfg)
param->ch_cfg = param_ini.ch_cfg;
memset(¶m->ch_info, 0, sizeof(param->ch_info));
memset(¶m->pub_info, 0, sizeof(param->pub_info));
param->mode = param_ini.mode;
return 0;
}
static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)
{
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg;
const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
if (ch >= RTW89_DMA_CH_NUM)
return -EINVAL;
if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) ||
ch_cfg[ch].max > pub_cfg->pub_max)
return -EINVAL;
if (ch_cfg[ch].grp >= grp_num)
return -EINVAL;
return 0;
}
static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)
{
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg;
struct rtw89_hfc_pub_info *info = ¶m->pub_info;
if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) {
if (rtwdev->chip->chip_id == RTL8852A)
return 0;
else
return -EFAULT;
}
return 0;
}
static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)
{
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max)
return -EFAULT;
return 0;
}
static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_page_regs *regs = chip->page_regs;
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
int ret = 0;
u32 val = 0;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
ret = hfc_ch_cfg_chk(rtwdev, ch);
if (ret)
return ret;
if (ch > RTW89_DMA_B1HI)
return -EINVAL;
val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) |
u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) |
(cfg[ch].grp ? B_AX_GRP : 0);
rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
return 0;
}
static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_page_regs *regs = chip->page_regs;
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
struct rtw89_hfc_ch_info *info = param->ch_info;
const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
u32 val;
u32 ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
if (ch > RTW89_DMA_H2C)
return -EINVAL;
val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK);
if (ch < RTW89_DMA_H2C)
info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK);
else
info[ch].used = cfg[ch].min - info[ch].aval;
return 0;
}
static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_page_regs *regs = chip->page_regs;
const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
u32 val;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
ret = hfc_pub_cfg_chk(rtwdev);
if (ret)
return ret;
val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) |
u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK);
rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK);
rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
return 0;
}
static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_page_regs *regs = chip->page_regs;
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
struct rtw89_hfc_pub_info *info = ¶m->pub_info;
u32 val;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
val = rtw89_read32(rtwdev, regs->pub_page_info1);
info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK);
info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK);
val = rtw89_read32(rtwdev, regs->pub_page_info3);
info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK);
info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK);
info->pub_aval =
u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
B_AX_PUB_AVAL_PG_MASK);
info->wp_aval =
u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
B_AX_WP_AVAL_PG_MASK);
val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
param->en = val & B_AX_HCI_FC_EN ? 1 : 0;
param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0;
param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK);
prec_cfg->ch011_full_cond =
u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK);
prec_cfg->h2c_full_cond =
u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK);
prec_cfg->wp_ch07_full_cond =
u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
prec_cfg->wp_ch811_full_cond =
u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK);
prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK);
val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK);
val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK);
prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK);
val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK);
val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK);
pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK);
ret = hfc_pub_info_chk(rtwdev);
if (param->en && ret)
return ret;
return 0;
}
static void hfc_h2c_cfg(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_page_regs *regs = chip->page_regs;
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
u32 val;
val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
B_AX_HCI_FC_CH12_FULL_COND_MASK,
prec_cfg->h2c_full_cond);
}
static void hfc_mix_cfg(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_page_regs *regs = chip->page_regs;
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
u32 val;
val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) |
u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK);
rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
val = u32_encode_bits(prec_cfg->wp_ch07_prec,
B_AX_PREC_PAGE_WP_CH07_MASK) |
u32_encode_bits(prec_cfg->wp_ch811_prec,
B_AX_PREC_PAGE_WP_CH811_MASK);
rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
param->mode, B_AX_HCI_FC_MODE_MASK);
val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
B_AX_HCI_FC_WD_FULL_COND_MASK);
val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
B_AX_HCI_FC_CH12_FULL_COND_MASK);
val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
}
static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_page_regs *regs = chip->page_regs;
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
u32 val;
val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
param->en = en;
param->h2c_en = h2c_en;
val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN);
val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) :
(val & ~B_AX_HCI_FC_CH12_EN);
rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
}
static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)
{
u8 ch;
u32 ret = 0;
if (reset)
ret = hfc_reset_param(rtwdev);
if (ret)
return ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
hfc_func_en(rtwdev, false, false);
if (!en && h2c_en) {
hfc_h2c_cfg(rtwdev);
hfc_func_en(rtwdev, en, h2c_en);
return ret;
}
for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) {
ret = hfc_ch_ctrl(rtwdev, ch);
if (ret)
return ret;
}
ret = hfc_pub_ctrl(rtwdev);
if (ret)
return ret;
hfc_mix_cfg(rtwdev);
if (en || h2c_en) {
hfc_func_en(rtwdev, en, h2c_en);
udelay(10);
}
for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) {
ret = hfc_upd_ch_info(rtwdev, ch);
if (ret)
return ret;
}
ret = hfc_upd_mix_info(rtwdev);
return ret;
}
#define PWR_POLL_CNT 2000
static int pwr_cmd_poll(struct rtw89_dev *rtwdev,
const struct rtw89_pwr_cfg *cfg)
{
u8 val = 0;
int ret;
u32 addr = cfg->base == PWR_INTF_MSK_SDIO ?
cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr;
ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);
if (!ret)
return 0;
rtw89_warn(rtwdev, "[ERR] Polling timeout\n");
rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
return -EBUSY;
}
static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,
u8 intf_msk, const struct rtw89_pwr_cfg *cfg)
{
const struct rtw89_pwr_cfg *cur_cfg;
u32 addr;
u8 val;
for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) {
if (!(cur_cfg->intf_msk & intf_msk) ||
!(cur_cfg->cv_msk & cv_msk))
continue;
switch (cur_cfg->cmd) {
case PWR_CMD_WRITE:
addr = cur_cfg->addr;
if (cur_cfg->base == PWR_BASE_SDIO)
addr |= SDIO_LOCAL_BASE_ADDR;
val = rtw89_read8(rtwdev, addr);
val &= ~(cur_cfg->msk);
val |= (cur_cfg->val & cur_cfg->msk);
rtw89_write8(rtwdev, addr, val);
break;
case PWR_CMD_POLL:
if (pwr_cmd_poll(rtwdev, cur_cfg))
return -EBUSY;
break;
case PWR_CMD_DELAY:
if (cur_cfg->val == PWR_DELAY_US)
udelay(cur_cfg->addr);
else
fsleep_alt(cur_cfg->addr * 1000);
break;
default:
return -EINVAL;
}
}
return 0;
}
static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,
const struct rtw89_pwr_cfg * const *cfg_seq)
{
int ret;
for (; *cfg_seq; cfg_seq++) {
ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
PWR_INTF_MSK_PCIE, *cfg_seq);
if (ret)
return -EBUSY;
}
return 0;
}
static enum rtw89_rpwm_req_pwr_state
rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)
{
enum rtw89_rpwm_req_pwr_state state;
switch (rtwdev->ps_mode) {
case RTW89_PS_MODE_RFOFF:
state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF;
break;
case RTW89_PS_MODE_CLK_GATED:
state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED;
break;
case RTW89_PS_MODE_PWR_GATED:
state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED;
break;
default:
state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE;
break;
}
return state;
}
static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,
enum rtw89_rpwm_req_pwr_state req_pwr_state,
bool notify_wake)
{
u16 request;
spin_lock_bh(&rtwdev->rpwm_lock);
request = rtw89_read16(rtwdev, R_AX_RPWM);
request ^= request | PS_RPWM_TOGGLE;
request |= req_pwr_state;
if (notify_wake) {
request |= PS_RPWM_NOTIFY_WAKE;
} else {
rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
RPWM_SEQ_NUM_MAX;
request |= FIELD_PREP(PS_RPWM_SEQ_NUM,
rtwdev->mac.rpwm_seq_num);
if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED)
request |= PS_RPWM_ACK;
}
rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
spin_unlock_bh(&rtwdev->rpwm_lock);
}
static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,
enum rtw89_rpwm_req_pwr_state req_pwr_state)
{
bool request_deep_mode;
bool in_deep_mode;
u8 rpwm_req_num;
u8 cpwm_rsp_seq;
u8 cpwm_seq;
u8 cpwm_status;
if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED)
request_deep_mode = true;
else
request_deep_mode = false;
if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))
in_deep_mode = true;
else
in_deep_mode = false;
if (request_deep_mode != in_deep_mode)
return -EPERM;
if (request_deep_mode)
return 0;
rpwm_req_num = rtwdev->mac.rpwm_seq_num;
cpwm_rsp_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM,
PS_CPWM_RSP_SEQ_NUM);
if (rpwm_req_num != cpwm_rsp_seq)
return -EPERM;
rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
CPWM_SEQ_NUM_MAX;
cpwm_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_SEQ_NUM);
if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
return -EPERM;