RTL Code Coverage Hole in cv32e40p_ID_stage module line 872

[YoannPruvost]

Component

Component:RTL

Issue Description

One of the possible combination in the if statement line 872 of cv32e40p_ID_stage was not covered during all the simulation non-regressions.

After analysis we suspected that this scenario was in fact unreachable.
Siemens Questa Static formal tool was used to prove that this scenario was unreachable. For this scenario a dedicated assertion was written, named assert_unreachable_id_872.

All information necessary to reproduce and analyze our work with formal can be found in the ReadMe in the cv32e40p/scripts/formal folder

As it was too late to implement a fix in the RTL due to long RISC-V ISA Formal Verification runs and requiring to update all waivers files as well, it has been decided to waive this scenario hole in v2.