Testfloat on Verilator not progressing

[davidharrishmc]

I started writing sim-testfloat-verilator. It now compiles but seems to hang in the first test.

harris@chips:/cvw/sim$ ./sim-testfloat-verilator
harris@chips:/cvw/sim$ time obj_dir/Vtestbenchfp
Running ui32_to_f128_rne.tv vectors
...(no progress)

[davidharrishmc]

Now invokes with
wsim -s verilator -t testbench_fp fdqh_ieee_rv64gc cvtint

Still hangs at
Running ui32_to_f128_rne.tv vectors

[davidharrishmc]

After cleaning up some lint issues,

wsim --tb testbench_fp --sim verilator rv32gc add

fails with

Running f64_add_rne.tv vectors 

Error in f64_add_rne.tv
TestNum          0 VectorNum          0 OpCtrl 6
inputs: ffffffff3f908000 0000000000000000 0000000000000000
SrcA: 00000000
 Res: ffffffff00000000 00
 Expected: 000000000007ffff 01

The reason is that readvectors is triggered (@VectorNum) before Unit, Fmt, OpCtrl) have their correct values, so the wrong vector is read. In contrast, Questa receives

# TestNum          0 VectorNum          0 OpCtrl 6
# inputs: b68ffff8000000ff 3ff0000000000000 3f9080000007ffff
# SrcA: xxxxxxxx
#  Res: 3f9080000007ffff 01
#  Expected: 3f9080000007ffff 01

[davidharrishmc]

Made some progress with commit 459eaae
However, the sequencing of testbench_fp is highly messed up. The module will likely require an entire refactoring to fix this. Readvectors may need to be removed as a module and incorporated into the main module. In the same always_ff @(posedge clk) block that loads vectors or advances the vector number, the readvectors logic may need to assign the new inputs and expected output.