AEEE-Summer School FPGA Camp

This is a repository to deliver the 2024 FPGA Camp Training Material on July 9-11, 2024. Please DO NOT distribute this document for any commercial purposes.

Tools Version

Please follow the installation guide to install Vivado or Vitis on your Windows or Linux Machine.

For Linux Machine, please follow this guide to install the vitis vision library

For Windows Machine, please follow this guide to intall the vitis vision library.

If you have a PYNQ Supported Board at hand, please download and write the image into the SD Card. The PYNQ getting started guide can be found here.

• Vitis 2023.1~2024.1
• Vivado 2023.1~2024.1
• PYNQ v2.7,v3.0

Lab Steps

Project-Based Learning Material Lab Steps

Remote Lab Usage

Agenda

DATE	Time	Subject	Resource
Tuesday, July 9	9:30 AM-11:30 AM	Opening Ceremony of Summer School FPGA Camp
		Reviewing the Basics to Master the New: Principles and Structure of FPGA	FPGA_Vivado_Flow
	2:00 PM-5:00 PM	FPGA Design Optimization: From Static Timing Analysis to Timing Closure	FPGA_Vivado_Flow
		Starting from Scratch: Developing Vision Processing Kernels with Vitis Libraries	Vitis Vision Library
		Lab1: Writing Your Vision Processing Kernel	Lab1_sobel
Wednesday, July 10	9:30 AM-11:30 AM	PYNQ Framework: Building Customized Hardware and Software Co-Design	PYNQ Home
		Efficient IP Verification Process under the PYNQ Framework
		Lab2 : Verify the Adder IP Wapped with AXI-Lite Interface	Lab2_add_axilite
	2:00 PM-5:00 PM	Introduction to MPSoC: Design Process Based on Kria-SoM KV260	UG1089
		Homework: Writing Your HLS Convolution Filter
Thursday, July 11	9:30 AM-11:30 AM	Diving Deep into High-Performance Vitis HLS Design Methodology	WP554
		Best Practices for HLS Convolution Filter Design
		Lab3: Writing Your HLS Convolution Filter	lab3_conv_filter
	2:00 PM-5:00 PM	Comprehensive Analysis of the New Generation Products and Tools Updates
		FPGA Competition Mobilization and Problem Statement Interpretation

Homework

Lab1 Basic Version: Modify the visual library routines in Lab1. You can change the code to use input images of different sizes. The final assessment standard is based on updating the demonstration results in Jupyter notebook and HLS src code.

Lab1 Advanced Version: Add the resize or cv2color operator and link it with the Sobel operator with any interface to achieve image processing.

Lab2 Basic Version: Replace the adder function in the RTL IP core with any other algorithm. Use the AXI lite protocol as the interface, with the ILA waveform diagram and Jupyter notebook as the main evaluation criteria.

Lab2 Advanced Version: Use the AXI bus or AXIS bus to achieve functional verification of any RTL IP under the PYNQ framework.

Lab3 Homework Choose an arbitrary HLS design and optimize it according to design rules. Compare the results before and after optimization, and briefly explain the reasons for the changes.

Submission

• Deadline: 18th July
• Submission format:
  • Github or Gitee repository with project souce code，Please submit using the same directory structure as the experimentPlease use the same project hiher
• E-mail Notification: [email protected]

Additional Material

1. High Level Synthesis Material
2. Download Vivado Software
3. Download Vitis Unified Software
4. Vitis Unified Software Documentation
5. Vitis Community Forum
6. Accelerating OpenCV Applications with Zynq-7000 All Programmable SoC using Vivado HLS Video Libraries
7. Vivado FPGA Design Flow on Spartan and Zynq
8. High-Level-Synthesis Design Flow on ZYNQ
9. Vitis HLS: High-Performance Design Using Task-level Parallelism
10. Vitis Unified Software Platform Documentation: Application Acceleration Development
11. Vitis Application Development Flow
12. Data Center Acceleration Terminology