make Gowin boards work with Apicula #603
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LGTM. But for 20k, 25k BaseSoC call must be update with the toolchain param. |
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Yes several Gowin boards remain to be tested, currently only 4K actually works completely, some of the others might be fine if I take a target that doesn't use advanced IO things for memory. |
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Alright so the current status is:
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pepijndevos
changed the title
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I didn't break CI right? Any commit guidelines I should follow? I think this is pretty much done on the LiteX side, and I'll be working on the Apicula/Nextpnr side to improve things there so we can hopefully use SDRAM. |
| if toolchain=="gowin": | ||
| # this is just a software check that doesn't translate to hardware | ||
| # apicula does not implement this check, so beware of bricking your board | ||
| self.toolchain.options["use_mode_as_gpio"] = 1 | ||
| else: | ||
| # yosys doesn't know that 4K doesn't have lutram so we tell it | ||
| self.toolchain._synth_opts += " -nolutram" | ||
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A last question here: maybe is it possible to move this part to apicula toolchain? This avoid to have to copy/paste these lines for all boards with this trick.
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It'd have to be spread across several tools I guess.
Yosys is currently oblivious to the specific device it's synthesizing for, so you could add a -family flag there or something but that doesn't really have any advantage over -nolutram until there are more significant differences.
We could add a --mode-as-gpio flag to the packer that implements the check, but like the comment said it doesn't translate to anything in hardware. It's more of a "are you sure you want to do this" thing. Given that you wrote the constraints file, I would assume the answer is "yes". All of the other as-gpio flags actually change bits to switch the functionality.
| self.specials += [ | ||
| Instance("DHCEN", | ||
| i_CLKIN = self.cd_sys2x_i.clk, | ||
| i_CE = self.stop, | ||
| o_CLKOUT = self.cd_sys2x.clk), | ||
| Instance("CLKDIV", | ||
| p_DIV_MODE = "2", | ||
| i_CALIB = 0, | ||
| i_HCLKIN = self.cd_sys2x.clk, | ||
| i_RESETN = ~self.reset, | ||
| o_CLKOUT = self.cd_sys.clk), | ||
| AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset), | ||
| ] |
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This piece of code is required to use external DDR. Is the build end successfully?
Also when with_clk reset signal isn't driven by self.rst nor by self.reset
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Ah, maybe it should be gated on integrated_main_ram_size then? I've only tested it without sdram because Apicula doesn't support the magic constraints yet.
In the clkdivless case it's exactly the same as Tang Nano 20k.
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How does this sys2x domain actually get used? It doesn't seem to be passed to the sdram directly
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This clock source is used by the litedram phy
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No this PR doesn't break anything. CI fails due to a recent litedram update. |
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I see ci is fixed. All good now? |
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Applied with some modifications. Thanks @pepijndevos |
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| if dock == "lite": | ||
| with_led_chaser = False # No leds on core board nor on dock lite. | ||
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| # CRG -------------------------------------------------------------------------------------- | ||
| self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal) | ||
| with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0) | ||
| assert not (toolchain == "apicula" and with_dram) |
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So we need to remove this assertion once Apicula supports sdram right
Thanks to enjoy-digital/litex#2036 by @Mai-Lapyst LiteX supports Apicula with the Himaechel target now, but it appears that the boards do not yet work correctly.
This is a WIP PR to try and fix those. I figured I'd put it out there to avoid duplicating work with Mai.
So far I've been mostly threading
toolchainthrough to the platform. Currently it fails to connect the RAM chips with their SERDES and SiP IO stuff. Some of that may be a more long-term project.Depends on enjoy-digital/litex#2042