Cleanup of some latent verible changes.

openhwgroup · Jul 13, 2023 · 150394c · 150394c
1 parent 02ef8c6
commit 150394c
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Showing 2 changed files with 21 additions and 16 deletions.
diff --git a/rtl/core-v-mcu/fc/cv32e40p_fp_wrapper.sv b/rtl/core-v-mcu/fc/cv32e40p_fp_wrapper.sv
@@ -72,14 +72,19 @@ module cv32e40p_fp_wrapper
   // Implementation (number of registers etc)
   localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
   PipeRegs:  '{// FP32, FP64, FP16, FP8, FP16alt
-  '{C_LAT_FP32, C_LAT_FP64, C_LAT_FP16, C_LAT_FP8, C_LAT_FP16ALT},  // ADDMUL
-  '{default: C_LAT_DIVSQRT},  // DIVSQRT
-  '{default: C_LAT_NONCOMP},  // NONCOMP
-  '{default: C_LAT_CONV}},  // CONV
-  UnitTypes: '{'{default: fpnew_pkg::MERGED},  // ADDMUL
-  '{default: fpnew_pkg::MERGED},  // DIVSQRT
-  '{default: fpnew_pkg::PARALLEL},  // NONCOMP
-  '{default: fpnew_pkg::MERGED}},  // CONV
+      '{
+          C_LAT_FP32, C_LAT_FP64, C_LAT_FP16, C_LAT_FP8, C_LAT_FP16ALT
+      },  // ADDMUL
+      '{default: C_LAT_DIVSQRT},  // DIVSQRT
+      '{default: C_LAT_NONCOMP},  // NONCOMP
+      '{default: C_LAT_CONV}
+  },  // CONV
+  UnitTypes: '{
+      '{default: fpnew_pkg::MERGED},  // ADDMUL
+      '{default: fpnew_pkg::MERGED},  // DIVSQRT
+      '{default: fpnew_pkg::PARALLEL},  // NONCOMP
+      '{default: fpnew_pkg::MERGED}
+  },  // CONV
   PipeConfig: fpnew_pkg::AFTER};
 
   //---------------

diff --git a/rtl/core-v-mcu/soc/soc_interconnect_wrap.sv b/rtl/core-v-mcu/soc/soc_interconnect_wrap.sv
@@ -70,9 +70,9 @@ module soc_interconnect_wrap
   //Everything that is not routed to port 1 or 2 ends up in port 0 by default
   localparam addr_map_rule_t [NR_RULES_L2_DEMUX-1:0] L2_DEMUX_RULES = '{
       '{ idx: 1 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK0_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR} , //Both , bank0 and bank1 are in the  same address block
-  '{ idx: 1 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR      , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR}      ,
-        '{ idx: 1 , start_addr: `EFPGA_ASYNC_APB_START_ADDR      , end_addr: `EFPGA_ASYNC_APB_END_ADDR},
-        '{ idx: 2 , start_addr: `SOC_MEM_MAP_TCDM_START_ADDR          , end_addr: `SOC_MEM_MAP_TCDM_END_ADDR }
+      '{ idx: 1 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR      , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR}      ,
+      '{ idx: 1 , start_addr: `EFPGA_ASYNC_APB_START_ADDR      , end_addr: `EFPGA_ASYNC_APB_END_ADDR},
+      '{ idx: 2 , start_addr: `SOC_MEM_MAP_TCDM_START_ADDR          , end_addr: `SOC_MEM_MAP_TCDM_END_ADDR }
   };
 
   localparam NR_RULES_INTERLEAVED_REGION = 1;
@@ -83,15 +83,15 @@ module soc_interconnect_wrap
   localparam NR_RULES_CONTIG_CROSSBAR = 4;
   localparam addr_map_rule_t [NR_RULES_CONTIG_CROSSBAR-1:0] CONTIGUOUS_CROSSBAR_RULES = '{
       '{ idx: 0 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK0_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK0_END_ADDR} ,
-        '{ idx: 1 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK1_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR} ,
-        '{ idx: 2 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR      , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR},
-        '{ idx: 3 , start_addr: `EFPGA_ASYNC_APB_START_ADDR      , end_addr: `EFPGA_ASYNC_APB_END_ADDR}
+      '{ idx: 1 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK1_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR} ,
+      '{ idx: 2 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR      , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR},
+      '{ idx: 3 , start_addr: `EFPGA_ASYNC_APB_START_ADDR      , end_addr: `EFPGA_ASYNC_APB_END_ADDR}
   };
 
   localparam NR_RULES_AXI_CROSSBAR = 1;
   localparam addr_map_rule_t [NR_RULES_AXI_CROSSBAR-1:0] AXI_CROSSBAR_RULES = '{
-  //      '{ idx: 0, start_addr: `SOC_MEM_MAP_AXI_PLUG_START_ADDR,    end_addr: `SOC_MEM_MAP_AXI_PLUG_END_ADDR},
-  '{ idx: 0, start_addr: `SOC_MEM_MAP_PERIPHERALS_START_ADDR, end_addr: `SOC_MEM_MAP_PERIPHERALS_END_ADDR}
+      //'{ idx: 0, start_addr: `SOC_MEM_MAP_AXI_PLUG_START_ADDR,    end_addr: `SOC_MEM_MAP_AXI_PLUG_END_ADDR},
+      '{ idx: 0, start_addr: `SOC_MEM_MAP_PERIPHERALS_START_ADDR, end_addr: `SOC_MEM_MAP_PERIPHERALS_END_ADDR}
   };
 
   //For legacy reasons, the fc_data port can alias the address prefix 0x000 to 0x1c0. E.g. an access to 0x00001234 is