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    • mor1kx

      Public
      mor1kx - an OpenRISC 1000 processor IP core
      Verilog
      Other
      146488295Updated Sep 9, 2024Sep 9, 2024
    • or1ksim

      Public
      The OpenRISC 1000 architectural simulator
      C
      GNU General Public License v3.0
      436941Updated Aug 26, 2024Aug 26, 2024
    • Tcl
      7200Updated Aug 14, 2024Aug 14, 2024
    • OR1K Common Headers
      Python
      2000Updated Aug 14, 2024Aug 14, 2024
    • Copy of the old OpenCores OpenRISC Subversion
      C
      21500Updated Aug 14, 2024Aug 14, 2024
    • uClibc for OpenRISC 1000
      C
      GNU Lesser General Public License v2.1
      12000Updated Aug 14, 2024Aug 14, 2024
    • tutorials

      Public
      OpenRISC Tutorials
      Makefile
      204080Updated Aug 14, 2024Aug 14, 2024
    • linux

      Public
      Linux kernel source tree
      C
      Other
      53k2911Updated May 14, 2024May 14, 2024
    • glibc port for or1k
      C
      GNU General Public License v2.0
      9300Updated Apr 4, 2024Apr 4, 2024
    • intgen

      Public
      An verilog core for testing CPU interrupts
      Verilog
      4200Updated Sep 10, 2023Sep 10, 2023
    • Source for openrisc.io
      HTML
      91301Updated Jul 12, 2023Jul 12, 2023
    • Unified OpenRISC 1000 test suite
      Assembly
      11810Updated Jun 24, 2023Jun 24, 2023
    • or1k-gcc

      Public
      GCC port for OpenRISC 1000
      GNU General Public License v2.0
      362300Updated Mar 4, 2022Mar 4, 2022
    • newlib

      Public
      newlib OpenRISC development
      C
      GNU General Public License v2.0
      242440Updated Mar 4, 2022Mar 4, 2022
    • Binutils and gdb fork for OpenRISC
      C
      GNU General Public License v2.0
      12520Updated Mar 2, 2022Mar 2, 2022
    • doc

      Public
      Misc documentation and specifications
      101100Updated Feb 26, 2022Feb 26, 2022
    • OpenRISC processor IP core based on Tomasulo algorithm
      Verilog
      Other
      142910Updated Feb 18, 2022Feb 18, 2022
    • mor1kx OpenRISC generic test harness support verilator and iverilog
      Verilog
      7100Updated Feb 19, 2021Feb 19, 2021
    • A small suite of scripts and patches for building musl libc cross compilers.
      Shell
      70402Updated Nov 1, 2020Nov 1, 2020
    • Core description files for FuseSoC
      Verilog
      78123122Updated Jun 26, 2020Jun 26, 2020
    • gcc

      Public archive
      This is not the project you are looking for check openrisc/or1k-gcc.
      C
      GNU General Public License v2.0
      4.4k000Updated Dec 13, 2018Dec 13, 2018
    • llvm-or1k

      Public
      LLVM backend for OpenRISC 1000
      LLVM
      Other
      132500Updated Apr 6, 2018Apr 6, 2018
    • Clang for OpenRISC 1000
      C++
      Other
      9700Updated Mar 30, 2018Mar 30, 2018
    • ompic

      Public
      Open Multi-Processor Interrupt Controller - for OpenRISC
      Verilog
      7600Updated Oct 7, 2017Oct 7, 2017
    • Community Wiki clone
      7110Updated Oct 17, 2016Oct 17, 2016
    • barebox

      Public
      OpenRISC fork of barebox
      C
      Other
      9400Updated Mar 21, 2016Mar 21, 2016
    • Fork of the RTEMS source builder (RSB)
      Python
      3100Updated Mar 20, 2016Mar 20, 2016
    • or1k-src

      Public
      OpenRISC 1000 port for sourceware.org's src tree (binutils, gdb, newlib, etc.)
      C
      GNU General Public License v2.0
      322010Updated Mar 12, 2016Mar 12, 2016
    • or1200

      Public
      OpenRISC 1200 implementation
      Verilog
      7215710Updated Nov 11, 2015Nov 11, 2015
    • Zero-cost (Itanium ABI) exception handling library for OpenRISC 1000
      C++
      75000Updated Jul 24, 2015Jul 24, 2015