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Proper fix for the previous null derefs, reducing indirections
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radare committed Feb 15, 2023
1 parent 2491f61 commit df15299
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Showing 4 changed files with 12 additions and 15 deletions.
15 changes: 6 additions & 9 deletions libr/anal/fcn.c
Original file line number Diff line number Diff line change
Expand Up @@ -570,16 +570,13 @@ static int fcn_recurse(RAnal *anal, RAnalFunction *fcn, ut64 addr, ut64 len, int
} delay = {
0
};
if (anal->cur == NULL) {
R_LOG_WARN ("fcn.recurse found anal.cur is nul");
return R_ANAL_RET_ERROR;
}
bool arch_destroys_dst = does_arch_destroys_dst (anal->cur->arch);
const bool is_arm = anal->cur->arch && !strncmp (anal->cur->arch, "arm", 3);
const bool is_v850 = is_arm ? false: (anal->cur->arch && (!strncmp (anal->cur->arch, "v850", 4) || !strncmp (anal->coreb.cfgGet (anal->coreb.core, "asm.cpu"), "v850", 4)));
const bool is_x86 = is_arm ? false: anal->cur->arch && !strncmp (anal->cur->arch, "x86", 3);
const char *arch = anal->config? anal->config->arch: R_SYS_ARCH;
bool arch_destroys_dst = does_arch_destroys_dst (arch);
const bool is_arm = !strncmp (arch, "arm", 3);
const bool is_v850 = is_arm ? false: (arch && (!strncmp (arch, "v850", 4) || !strncmp (anal->coreb.cfgGet (anal->coreb.core, "asm.cpu"), "v850", 4)));
const bool is_x86 = is_arm ? false: arch && !strncmp (arch, "x86", 3);
const bool is_amd64 = is_x86 ? fcn->cc && !strcmp (fcn->cc, "amd64") : false;
const bool is_dalvik = is_x86 ? false : anal->cur->arch && !strncmp (anal->cur->arch, "dalvik", 6);
const bool is_dalvik = is_x86 ? false : arch && !strncmp (arch, "dalvik", 6);
const bool propagate_noreturn = anal->opt.propagate_noreturn;

if (r_cons_is_breaked ()) {
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2 changes: 1 addition & 1 deletion libr/anal/var.c
Original file line number Diff line number Diff line change
Expand Up @@ -1145,7 +1145,7 @@ static bool is_used_like_arg(const char *regname, const char *opsreg, const char
}
//fallthrough
default:
if (op_affect_dst (op) && arch_destroys_dst (anal->cur->arch)) {
if (op_affect_dst (op) && arch_destroys_dst (anal->config->arch)) {
if (is_reg_in_src (regname, anal, op)) {
return true;
}
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2 changes: 1 addition & 1 deletion libr/anal/vtable.c
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ R_API bool r_anal_vtable_begin(RAnal *anal, RVTableContext *context) {
context->anal = anal;
context->abi = anal->cxxabi;
context->word_size = (ut8) (anal->config->bits / 8);
const bool is_arm = anal->cur && anal->cur->arch && r_str_startswith (anal->cur->arch, "arm");
const bool is_arm = anal->config->arch && r_str_startswith (anal->config->arch, "arm");
if (is_arm && context->word_size < 4) {
context->word_size = 4;
}
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8 changes: 4 additions & 4 deletions libr/core/canal.c
Original file line number Diff line number Diff line change
Expand Up @@ -5444,8 +5444,8 @@ R_API void r_core_anal_esil(RCore *core, const char *str /* len */, const char *
r_cons_break_push (cccb, core);

int arch = -1;
if (!strcmp (core->anal->cur->arch, "arm")) {
switch (core->anal->cur->bits) {
if (!strcmp (core->anal->config->arch, "arm")) {
switch (core->anal->config->bits) {
case 64: arch = R2_ARCH_ARM64; break;
case 32: arch = R2_ARCH_ARM32; break;
case 16: arch = R2_ARCH_THUMB; break;
Expand All @@ -5455,7 +5455,7 @@ R_API void r_core_anal_esil(RCore *core, const char *str /* len */, const char *

ut64 gp = r_config_get_i (core->config, "anal.gp");
const char *gp_reg = NULL;
if (!strcmp (core->anal->cur->arch, "mips")) {
if (!strcmp (core->anal->config->arch, "mips")) {
gp_reg = "gp";
arch = R2_ARCH_MIPS;
}
Expand Down Expand Up @@ -5612,7 +5612,7 @@ R_API void r_core_anal_esil(RCore *core, const char *str /* len */, const char *
switch (op.type) {
case R_ANAL_OP_TYPE_LEA:
// arm64
if (core->anal->cur && arch == R2_ARCH_ARM64) {
if (cur && arch == R2_ARCH_ARM64) {
if (CHECKREF (ESIL->cur)) {
r_anal_xrefs_set (core->anal, cur, ESIL->cur, R_ANAL_REF_TYPE_STRING | R_ANAL_REF_TYPE_READ);
}
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