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Set lr correctly in blx esil on arm #22377

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Set lr correctly in blx esil on arm #22377

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2 changes: 1 addition & 1 deletion libr/arch/p/arm/plugin_cs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2495,7 +2495,7 @@ static int analop_esil(RArchSession *as, RAnalOp *op, ut64 addr, const ut8 *buf,
break;
case ARM_INS_BL:
case ARM_INS_BLX:
r_strbuf_append (&op->esil, "pc,lr,:=,");
r_strbuf_appendf (&op->esil, "pc,%d,+,lr,:=,", thumb);
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Suggested change
r_strbuf_appendf (&op->esil, "pc,%d,+,lr,:=,", thumb);
r_strbuf_appendf (&op->esil, "pc,lr,:=,%d,tf,:=", thumb);

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what do you think about this solution? its working?

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if not we should probably considering checking for the thumb flag in the register set which is more correct for esil cnoncepts than using the hacky lower bit thing in the program counter

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Sorry, I got sidetracked from all this and am abroad at the moment so can't do much, but i'll defer to your experience here

/* fallthrough */
case ARM_INS_BX:
case ARM_INS_BXJ:
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