drm/vc4: Also power down the PLL core when resetting PHY

The current reset code doesn't actually stop the hdmi output.
That makes it difficult for displays to handle a mode set.

Powering down the PLL does actually remove the hdmi signal
and makes mode sets more reliable

Signed-off-by: Dom Cobley <[email protected]>

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

@@ -137,6 +137,7 @@
 #define VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS	BIT(13)
 #define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK		VC4_MASK(9, 0)
 
+#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN		BIT(4)
 #define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK	VC4_MASK(3, 2)
 #define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK		VC4_MASK(1, 0)
 
@@ -947,6 +948,7 @@ static void vc6_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)
 
 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
 	HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL, 0);
+	HDMI_WRITE(HDMI_TX_PHY_PLL_POST_KDIV, VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN);
 }
 
 void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,