mb/system76: Enable dGPUs

Change-Id: Ia0d6c952541cbd09d14e82336e6dc6d7d7d18b44 Signed-off-by: Tim Crawford <[email protected]>
system76 · Jan 23, 2023 · c6ef149 · c6ef149
1 parent 3f278aa
commit c6ef149
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Showing 56 changed files with 447 additions and 42 deletions.
diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

diff --git a/src/mainboard/system76/addw1/Makefile.inc b/src/mainboard/system76/addw1/Makefile.inc
@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

diff --git a/src/mainboard/system76/addw1/acpi/mainboard.asl b/src/mainboard/system76/addw1/acpi/mainboard.asl
@@ -1,11 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
+	}
 }
 
 Scope (\_GPE) {

diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
@@ -58,6 +58,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device

diff --git a/src/mainboard/system76/addw1/romstage.c b/src/mainboard/system76/addw1/romstage.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Disable higher memory speeds
 	memupd->FspmConfig.SaOcSupport = 0;
 

diff --git a/...ard/system76/addw1/include/variant/gpio.h → ...dw1/variants/addw1/include/variant/gpio.h b/...ard/system76/addw1/include/variant/gpio.h → ...dw1/variants/addw1/include/variant/gpio.h
@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65d11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif
diff --git a/...rd/system76/gaze15/include/variant/gpio.h → ...dw1/variants/addw2/include/variant/gpio.h b/...rd/system76/gaze15/include/variant/gpio.h → ...dw1/variants/addw2/include/variant/gpio.h
@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65e11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif
diff --git a/src/mainboard/system76/adl-p/Kconfig b/src/mainboard/system76/adl-p/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOAR
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_ORYP9
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER

diff --git a/src/mainboard/system76/adl-p/Makefile.inc b/src/mainboard/system76/adl-p/Makefile.inc
@@ -1,4 +1,5 @@
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

diff --git a/src/mainboard/system76/adl-p/acpi/mainboard.asl b/src/mainboard/system76/adl-p/acpi/mainboard.asl
@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#include <variant/gpio.h>
+#endif
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,11 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+		Scope (PEG2) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
 	}
 }
diff --git a/src/mainboard/system76/adl-p/variants/oryp9/include/variant/gpio.h b/src/mainboard/system76/adl-p/variants/oryp9/include/variant/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif
diff --git a/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb
@@ -18,13 +18,17 @@ chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0x65f5 inherit
 
-		device ref pcie5_0 off
+		device ref pcie5_0 on
 			# CPU PCIe RP#2 x8, Clock 3 (DGPU)
 			register "cpu_pcie_rp[CPU_RP(2)]" = "{
 				.clk_src = 3,
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref igpu on
 			register "ddi_portA_config" = "1"

diff --git a/src/mainboard/system76/adl-p/variants/oryp9/romstage.c b/src/mainboard/system76/adl-p/variants/oryp9/romstage.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -17,6 +19,17 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
 	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
 	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
 	mupd->FspmConfig.GpioOverride = 0;

diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE14 || BOARD_SYSTEM76_GAZE15
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD

diff --git a/src/mainboard/system76/gaze15/Makefile.inc b/src/mainboard/system76/gaze15/Makefile.inc
@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

diff --git a/src/mainboard/system76/gaze15/acpi/mainboard.asl b/src/mainboard/system76/gaze15/acpi/mainboard.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,6 +10,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 

diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
@@ -57,6 +57,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

diff --git a/src/mainboard/system76/gaze15/romstage.c b/src/mainboard/system76/gaze15/romstage.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }
diff --git a/...ard/system76/oryp6/include/variant/gpio.h → ...15/variants/gaze14/include/variant/gpio.h b/...ard/system76/oryp6/include/variant/gpio.h → ...15/variants/gaze14/include/variant/gpio.h
@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85501558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif
diff --git a/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h b/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85201558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/include/variant/dgpu.h b/src/mainboard/system76/gaze16/variants/gaze16-3050/include/variant/dgpu.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_DGPU_H
+#define VARIANT_DGPU_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x50151558
+
+#endif
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/include/variant/dgpu.h b/src/mainboard/system76/gaze16/variants/gaze16-3060/include/variant/dgpu.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_DGPU_H
+#define VARIANT_DGPU_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x50e11558
+
+#endif
diff --git a/src/mainboard/system76/gaze17/Kconfig b/src/mainboard/system76/gaze17/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD

diff --git a/src/mainboard/system76/gaze17/acpi/mainboard.asl b/src/mainboard/system76/gaze17/acpi/mainboard.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +10,8 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Scope (PEG2) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
 	}
 }
diff --git a/src/mainboard/system76/gaze17/devicetree.cb b/src/mainboard/system76/gaze17/devicetree.cb
@@ -60,13 +60,19 @@ chip soc/intel/alderlake
 	device domain 0 on
 		#From CPU EDS(TODO)
 		device ref system_agent on end
-		device ref pcie5_0 off
+		device ref pcie5_0 on
 			# PCIe PEG2 x8, Clock 3 (DGPU)
 			register "cpu_pcie_rp[CPU_RP(2)]" = "{
 				.clk_src = 3,
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"