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Update submodules.
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@wsnyder
wsnyder committed Aug 20, 2024
1 parent 2178e06 commit 647fb07
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Showing 3 changed files with 3 additions and 3 deletions.
2 changes: 1 addition & 1 deletion submodules/Cores-VeeR-EL2
Submodule Cores-VeeR-EL2 updated 20 files
+2 −2 .github/assets/riscv_dv/README.md
+14,438 −0 .github/assets/riscv_dv/uvm/test_riscv_user_mode_rand_test/asm_test/riscv_user_mode_rand_test_0.S
+13,849 −0 .github/assets/riscv_dv/uvm/test_riscv_user_mode_rand_test/asm_test/riscv_user_mode_rand_test_1.S
+13,913 −0 .github/assets/riscv_dv/uvm/test_riscv_user_mode_rand_test/asm_test/riscv_user_mode_rand_test_2.S
+14 −9 .github/scripts/run_regression_test.sh
+5 −1 .github/workflows/test-regression.yml
+7 −2 .github/workflows/test-riscof.yml
+23 −4 .github/workflows/test-riscv-dv.yml
+1 −1 configs/README.md
+0 −6 design/lib/beh_lib.sv
+ − docs/source/img/riscv-dv-flow.png
+1 −1 docs/source/index.md
+258 −0 docs/source/verification.md
+5 −24 testbench/jtagdpi/README.md
+0 −49 testbench/tb_top.sv
+0 −7 testbench/tests/dhry/README
+1 −1 third_party/riscv-dv
+14 −4 tools/riscv-dv/Makefile
+12 −2 tools/riscv-dv/riscv_core_setting.sv
+38 −0 tools/riscv-dv/testlist.yaml
2 changes: 1 addition & 1 deletion submodules/gtkwave
Submodule gtkwave updated 3 files
+11 −1 lib/libfst/fstapi.c
+1 −1 lib/libgtkwave/src/gw-fst-file.c
+8 −1 src/menu.c
2 changes: 1 addition & 1 deletion submodules/verilator
Submodule verilator updated 147 files

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